1. Field of the Invention
The present invention relates to the application of electronically programmable fuses (eFuse) in integrated circuits. An electronically programmable fuse is disclosed with a low voltage programming capability and differential sensing scheme.
2. Background of Invention
With continued scaling in semiconductor technologies to increasingly smaller geometries, on-chip eFuse implementations provide an attractive alternative to conventional fusing schemes for integrated circuits. In terms of area efficiency and performance impact eFuse technology presents a significant improvement over fuse technologies with optical based programming.
Programmable devices for integrated circuits require a dependable methodology for customizing a device in a repeatable and reliable manner. Fusing of programmable connections in microprocessors, FPGAs and other VLSI designs is a common technique to achieve the flexibility of programmability.
The eFuse device fabricated in silicon based integrated circuits is typically programmed using a large voltage, relative to the operating voltage of the integrated circuit, to melt and separate the fuse body material. This process changes the fuse material from a low resistance to a high resistance, which may be measured by “sensing” circuitry to determine whether or not the eFuse has been programmed.
As process technology for integrated circuits has progressed, maximum operating voltages have scaled commensurately downward with physical geometry, making it difficult to provide sufficient voltage to program the eFuse without damaging logic circuitry associated with the fuse bank. In addition, the current density requirements for metal interconnect layers used to supply eFuse programming currents are typically much greater than for signal interconnect lines. As such, fuse programming buses must be implemented with wide metal wires that consume a disproportionate amount of interconnect resources. Furthermore, eFuse devices may require multiple programming pulses to ensure adequate resistance levels for the eFuse device, thereby increasing programming and test time cycles. However, repeated programming may also lead to an unfused condition in the programmed fuse if a sufficiently high voltage is applied. In that instance, the heating associated with re-programming may cause the fuse material to rejoin thereby further degrading fuse related yield.
Common applications for e-Fuse technology include memory array redundancy, package identification coding and post-manufacture programming of logical functions. Since each eFuse is a single primitive device, additional logic and circuitry are necessary to facilitate programming and sensing.
The eFuse programming operation involves sending a large current through the fuse (e.g., 15 mA) for a sufficient time to dramatically change the fuse resistance from an unprogrammed resistance of about 150 Ω to a resistance of about 50 KΩ. Existing schemes require a high voltage (e.g., 3.3V) to achieve adequate fuse programming current such that all fuses are guaranteed to have a high post-programming resistance. Insufficient programming current may result in a number of fuses exhibiting much lower resistance (e.g., 1 KΩ), and the “yield” following the programming step will be limited by the “tail” of the Gaussian distribution of resulting fuse resistances. In addition, a high programming voltage requires thick-oxide transistors, which, in turn, require extra processing steps to implement. Programming the fuses with a low voltage would eliminate the need for thick-oxide transistors, however, the programming current achievable at low programming voltage limits the maximum post-programming resistance and often requires multiple programming pulses to achieve the desired post fuse programming resistance. In addition, a significant number of low post-programming resistance values can result, which significantly impacts post fuse-programming yield.
Further, the 3.3V supply requires a dedicated package pin and tester channel (for programming at the tester). The routing of the 3.3V signal must be wide, low-resistance metal. This 3.3V supply is on during programming, but off during sensing. Therefore the 3.3V supply must be switchable to support the fuse programming function after final packaging of the integrated circuit in a chip carrier module.
A “sense” circuit is required to discriminate between pre-programming and post-programming resistance, and to provide digital “0” or “1” outputs respectively. Single-ended sensing schemes are known, but they are limited to the minimum resistance they can sense. Consequently, these circuits are not viable if any fuse has a low post-programming resistance. The single-ended scheme also requires an analog current-source-control voltage to be generated and routed to each individual sense circuit. Finally, this technique exhibits very poor noise rejection properties for sensing in the field and high switching activity causes additional noise on the power supply distribution network of the integrated circuit.
For example, FIG. 1 depicts a prior art single-ended eFuse sense scheme. A reference circuit VrefGen 10 creates a voltage VRef to control individual sense-current transistors mPi, with one for each of many fuses Fi. The input of inverter I0 is shorted to the output, establishing a voltage Vm equal to the “trip point” of a latch that would be made of two inverters identical to I0 feeding each other; OpAmp A drives an inverting stage consisting of mPRef and RRef such that Vp has the same voltage as Vm. The OpAmp output voltage VRef then feeds sense-current transistors mPi (one for each fuse Fi), and each fuse presents voltage Vi=Ri IRef to its own sense latch, which consists of two cross coupled inverters identical to I0 feeding each other that are not shown.
As future technologies continue to scale downward in feature size, a potential drawback to the prior art approach is that random manufacturing process variations may cause each transistor mPi to have a unique threshold voltage, such that the sense current will differ from fuse to fuse (VRef is a low-overdrive analog signal). Another related concern is that gate leakage from the VRef signal through the gates of individual transistors mPi will limit how many fuses can share one large VrefGen circuit.
Differential sense schemes are known, and they are better able to handle the tail of the resistance value distribution, however, prior differential sensing techniques employ two fuses to achieve a single programmed value, and also require one large differential amplifier per programmed value, thereby increasing the overall area requirement for fuse programming and sensing operations.
Accordingly, a need exists for an eFuse capable of being programmed by a single low voltage pulse, which incorporates a sensing scheme less susceptible to noise and requires fewer circuit resources then conventional designs.